1. Field of the Invention
The present invention relates to a pulse phase difference detecting circuit and an A/D converter using the same.
2. Description of Related Art
In general, examples of A/D converters (ADCs: analog-to-digital converters) for converting analog signals into digital signals at high speed include a flash type A/D converter and a successive approximation type A/D converter. The flash type and successive approximation type A/D converters, however, require a large number of reference voltages and comparators corresponding to a given resolution, which results in an increase in circuit size and cost of a device. In order to improve the accuracy of each of the reference voltages and comparators, semiconductor processes and devices with excellent analog characteristics are required. Additionally, in order to prevent a fluctuation in electrical characteristics of ADCs due to a layout pattern, it is necessary to select a layout pattern from a library of hard macros, resulting in limitation in the degree of freedom of design such as layout placement.
In this regard, there is known an ADC achieving a reduction in cost and circuit size by utilizing the fact that a delay amount of a delay element has a voltage dependence (see Japanese Unexamined Patent Application Publication Nos. 03-125514 and 2004-357030). The ADC generates a pulse phase difference according to an input voltage serving as an analog signal, and detects the phase difference by using a digital circuit.
FIG. 9 shows a pulse phase difference detecting circuit disclosed in FIG. 1 of Japanese Unexamined Patent Application Publication No. 03-125514. The pulse phase difference detecting circuit includes a gate delay circuit 10 and a synchronizing pulse detecting circuit 20. In the gate delay circuit 10, an input pulse signal PA is input to an inverter 41, and the output of the inverter 41 is connected to the input of an inverter 42 and is output as an output pulse signal P1. Further, the outputs and the inputs of inverters 43 to 4L are connected in a similar manner, and the outputs of even-numbered inverters 44 to 4L are output as output pulse signals P2 to Pn, respectively. In other words, the output pulse signals P1 to Pn are generated using delay times caused by the inverters 41 to 4L.
The synchronizing pulse detecting circuit 20 includes D flip-flops (D-FFs: Delay flip-flops) 51 to 5n which receive the output pulse signals P1 to Pn, respectively, as data from the gate delay circuit 10, and which also receive a pulse signal PB as a clock. Further, the synchronizing pulse detecting circuit 20 includes an AND gate 61 which receives an output Q of the D-FF 51 and an inverted output −Q of the D-FF 52, and which outputs a synchronizing pulse signal P01. Furthermore, the synchronizing pulse detecting circuit 20 includes AND gates 62 to 6m that receive outputs Q and inverted outputs −Q of the D-FFs 52 to 5n, and output synchronizing pulse signals P02 to P0m, respectively, in a similar manner.
It is generally known that, when the power supply voltage of an inverter is varied, the amount of delay caused by the inverter varies. Specifically, an increase in the power supply voltage causes a reduction in the delay amount, and a reduction in the power supply voltage causes an increase in the delay amount. In the technology disclosed in Japanese Unexamined Patent Application Publication No. 03-125514, a reduction in the power supply voltage of each of the inverters 41 to 4L causes an increase in time for the input pulse signal PA to reach the inverter 4L. Meanwhile, an increase in the power supply voltage of each of the inverters 41 to 4L causes a reduction in time for the input signal PA to reach the inverter 4L. If a pulse position is converted into a digital form, the ADC can operate using the power supply voltage of each inverter as an analog input voltage.
In order to realize the ADC with a high resolution by using the pulse phase difference detecting circuit disclosed in Japanese Unexamined Patent Application Publication No. 03-125514, a number of delay units corresponding to the number of desired bits are required. Thus, as the bit rate becomes higher, a total delay time of the delay units increases, and a time period from when the input pulse signal PA is input until when the pulse position is detected (i.e., a so-called sampling time of the ADC) becomes longer. This makes it difficult to perform a high-speed operation.
FIGS. 1 to 4 of Japanese Unexamined Patent Application Publication No. 2004-357030 disclose a pulse phase difference detecting circuit including m number of inverters which have different inversion levels and which are connected between delay units each including a pair of inverters. This configuration achieves a high resolution corresponding to the number of log2m bits, without reducing the operation speed.
As disclosed in Japanese Unexamined Patent Application Publication Nos. 03-125514 and 2004-357030, each of the delay units includes a pair of inverters for the following reason. That is, if each of the delay units is composed of one inverter, the detection time varies depending on an output logic of an inverter pulse, due to the fact that a rise time (tr) at which the output of each inverter is switched from the low level to the high level is different from a fall time (tf) at which the output of each inverter is switched from the high level to the low level.
In view of the foregoing, the present inventor has studied on the pulse phase difference detecting circuit as follows. First, while it is necessary to detect an accurate pulse position in the ADC using the pulse phase difference detecting circuit, it is also necessary to secure a given data set time or data retention period so that a D-FF for detecting the pulse position can retrieve data. These factors are determined by a CMOS process.
Further, in order to achieve the ADC having a high operation speed, a high resolution, and a low voltage per 1 LSB, it is necessary to provide inverters having delay characteristics with a small delay time and a large delay variation with respect to a voltage per 1 LSB. For example, CMOS transistors configured to operate at a voltage close to a threshold voltage Vth may be used as the inverters having a large delay variation with respect to a voltage. When the inverters are used to operate at the voltage close to the threshold voltage Vth, however, the delay amount of the entire delay units increases and the sampling time of the ADC also increases, which makes it difficult to perform a high-speed operation. In addition, since the transistor operation at the voltage close to the threshold voltage Vth is unstable, the delay variation (jitter) of the inverter increases, which results in a reduction in conversion accuracy of the ADC. For this reason, inverters are generally configured to operate at a sufficiently high voltage so as to stabilize the transistor operation.
Meanwhile, when the inverters are configured to operate at a voltage at which the transistor operation is stabilized, the delay variation per single delay unit with respect to the power supply voltage of each of the inverters is reduced. If the delay variation per single delay unit with respect to the voltage of each inverter is smaller than the data set time or data retention period necessary for a D-FF to retrieve data, it is impossible for the D-FF to detect the delay variation with the delay unit defined as 1 LSB, namely, the pulse position per 1 LSB. Accordingly, in order to obtain a sufficient delay variation per single delay unit for the pulse position detection using a D-FF, multi-stage delay units for securing a delay time need to be connected in series at the previous stage of the pulse phase difference detecting circuit. A detailed description thereof will be given below.
In the ADC using the pulse phase difference detecting circuit, a time for executing the pulse position detection is set to be equal to a time for a pulse to travel through all the delay units, when the smallest delay corresponding to the upper limit of the input voltage of the ADC is obtained. Specifically, the time for executing the pulse position detection is set so that a pulse reaches the most significant bit (MSB) located at the head of the pulse phase difference detecting circuit in the case where the input voltage of the ADC corresponds to the upper limit. Furthermore, the time for executing the pulse position detection is set so that a pulse reaches the least significant bit (LSB) located at the back end of the pulse phase detecting circuit in the case where the input voltage of the ADC corresponds to the lower limit.
Assuming herein that “ΔT” represents a difference between the total delay amount of the delay units of the pulse phase difference detecting circuit at the input voltage corresponding to the upper limit and the total delay amount between the delay units of the pulse phase difference detecting circuit at the input voltage corresponding to the lower limit; “n” represents the number of bits of the ADC; “Td1” represents a delay amount per single delay unit at the time when the input voltage corresponds to the upper limit; and “Td2” represents a delay amount per single delay unit at the time when the input voltage corresponds to the lower limit, a relation ΔT=2n×(Td2−Td1) is satisfied. Thus, it is necessary to provide a delay time at the previous stage of the pulse phase difference detecting circuit by an amount corresponding to the difference ΔT between the total delay amounts.
For example, it is assumed that a 6-bit ADC having an accuracy of 1 LSB=10 mV at an input voltage in a range from 2.2 V to 1.6 V is designed by a CMOS process adopting a 0.35 μm rule. Further, it is herein assumed that the delay unit is formed of a pair of inverters. It is also assumed that each inverter includes a Pch transistor having a gate length L=1 μm and a gate width W=2 μm, and an Nch transistor having a gate length L=1 μm and a gate width W=1 μm. The delay amount of single delay unit composed of a pair of inverters has a voltage dependence as shown in FIG. 10. Specifically, the delay amount is about 1.2 ns when the input voltage is 2.2 V, and the delay amount is 2.3 ns when the input voltage is 1.6 V. In other words, the delay amount obtained when the input voltage is 1.6 V is about twice as large as the delay amount obtained when the input voltage is 2.2 V. In this case, the delay variation per single delay unit with respect to a change of 10 mV at the input voltage of 2.2 V is about 10 ps. Accordingly, when a D-FF is used, the delay variation corresponding to the change in input voltage value of about 2.2 V cannot be detected. Note that, under this condition, the difference ΔT between the total delay amount of the delay units of the pulse phase difference detecting circuit at the input voltage corresponding to the upper limit and the total delay amount of the delay units of the pulse phase difference detecting circuit at the input voltage corresponding to the lower limit is expressed as ΔT=(2.3−1.2) ns×64=70 ns.
Assuming that 64 delay units are connected to the previous stage of a pulse phase difference detection detecting unit composed of 64 delay units, when a pulse reaches the pulse phase difference detecting circuit, a delay variation corresponding to a change of 10 mV at the input voltage of 2.2 V is increased by an amount corresponding to about 10 ps×64=640 ps. Accordingly, a sufficient response time of a D-FF is secured. As a result, the pulse position corresponding to the change of 10 mV can be detected by the D-FF.